(1) Field of the Invention
The present invention relates generally to a silicon on silicon-germanium (SiGe) device and particularly to a method for reducing junction leakage current in an MOS device formed in strained silicon on SiGe.
(2) Description of the Prior Art
Continuous demand for improved performance in the electronics industry has been possible as a result of materials, equipment, and process advances related to silicon technology. However, economic and physical constraints are rendering further developments to conventional silicon technology unviable. To date, the performance of a semiconductor device has improved its performance by miniaturizing the dimensions and by increasing scale of integration. There has been therefore, in the last five years, a lot of discussion in trade journals on a new technology, strained-silicon transistors, that has potential use in the next CMOS (complimentary CMOS) generations. The strained-silicon (SS) transistor is fabricated on a silicon layer deposited on a substrate containing SiGe and utilizing the resulting lattice distortion in deposited silicon to achieve higher carrier mobility. With up to 4.2% lattice mismatch between relaxed Si and SiGe, silicon lattice when epitaxially deposited on relaxed SiGe gets stretched resulting in strained silicon. Electrons and holes in such strained silicon have a higher mobility than those in conventional unstrained silicon. If a transistor is fabricated using strained layer as the channel layer in a MOSFET device, the speed of the device is significantly increased. Up to 70% increase in electron mobility and 35% improvement in chip performance have been reported (J. G. Spooner, IBM reveals new strain of chip power, CNET News.com, Jun. 8, 2001).
SS technology is aimed at applications such as high performance electronics, both digital and analog; wireless ICs; high-end microprocessors used in servers; handheld devices requiring lower power consumption. The SS technology is not without its challenges, being quite new to the business. Some major ones are: dislocations in SS, maintaining the strain level through all the process steps in manufacturing, degradation of interface strain. In addition, the challenges faced by bulk silicon such as short channel effects, device isolation, CMOS integration issues are also applicable to strained silicon. The SS transistor technology being new, it does not have much prior art on fabrication processes described in the literature. The patents discussed in the following paragraphs pertain more to some process steps that are used in the conventional silicon transistor fabrication technology and are used in fabricating SS transistors and SiGe devices.
U.S. Pat. No. 6,235,567 B1 describes a process for forming SiGe, BiCMOS (bipolar CMOS) device on SOI (silicon-on-insulator). CMOS transistors are formed in a 0.1-0.2 μm thick silicon layer deposited on an SOI substrate. Bipolar SiGe transistors are formed in a nominally 0.5 μm thick epitaxial film. CMOS transistors are formed first and then covered with an insulating film. The insulating film is removed from the bipolar areas and an epitaxial SiGe layer is deposited on exposed silicon. Bipolar transistors are then formed in the epitaxial layer for the base and having an encapsulated structure for device insulation using shallow isolation trenches and the buried oxide.
U.S. Pat. No. 6,274,894 B1 describes a short-channel MOS transistor and a method of forming a low-band gap source and drain in such a device. A gate structure formed on a semiconductor substrate is covered on all sides with a dielectric layer. Shallow trenches are then etched on either side of the gate. A thin layer of a material, with band-gap lower than that of the substrate, is grown on the exposed semiconductor surfaces of the trench using selective epitaxial deposition. The lower band-gap material may be un-doped to be used as a buffer layer for inter-diffusion of dopants between source and drain regions; or it may be heavily doped with the same carrier type as the substrate and used as a halo region to reduce punch-through and threshold voltage lowering effects. The portion of the trench above the low-band gap layer is filled with semiconductor material doped with opposite carrier type than that of the substrate to form lightly doped drain regions of the source and drain.
U.S. Pat. No. 6,294,817 B1 describes a source/drain-on-insulator (S/DOI) FET and a method of fabrication using oxidized amorphous silicon. Shallow trench isolation partially surrounds each transistor. Typically for a single transistor, only one surface of each source and drain (S/D) region make direct contact to the semiconductor body; and these surfaces are on opposite side of the channel region of each transistor. One method of fabrication of forming S/D regions is to form an isolation structure around active areas in which transistor is to be formed. Trenches separated by portions of the body are then formed in the active areas. On the bottom surface of the trench, an insulating layer is deposited and then filled with a semiconductor material of a conductivity type opposite that of the semiconductor substrate. The semiconductor filled portion of each trench serves as a drain and/or source of an FET.
U.S. Pat. No. 6,306,723 B1 describes a method to form shallow trench isolations without chemical mechanical polishing. After depositing a pad oxide layer and a silicon nitride layer on a silicon substrate, trenches are formed into the silicon substrate to form shallow trench isolation. A liner oxide is then grown in the trenches followed by spacer oxide deposition over the silicon nitride layer and the liner oxide layer to partially fill the trenches. The spacer and liner oxide layers are anisotropically etched to form side-wall spacers within the trenches while exposing the bottom silicon surfaces. A silicon layer is then selectively grown on the exposed silicon surface to partially fill the trenches. A trench oxide layer is then formed over the silicon layer. The silicon nitride and pad oxide layers are then removed to complete shallow trench isolation formation.
It is to be noted here that none of these patents describes MOSFET device fabrication in strained-silicon on SiGe substrate. One limitation of a device featuring a p-n junction on strained Si/SiGe substrate is the higher junction leakage current compared to bulk Si, associated with the lower band gap of SiGe. As MOSFET features p-n junction in the form of source-to-substrate and drain-to-substrate, the leakage current problem can be dominant during reverse biasing of the drain junction;